One of the main markets for silicon-on-insulator (SOI) devices is high-temperature application. In the last decade, the technology advances to deep submicron era to improve device performance, lower power consumption, reduce occupied area, etc. This unavoidably results in the appearance of new phenomena or significant changes to existing ones. The question to be addressed is “how the progress in MOSFET technology affects the high-temperature behavior of the devices?” Indeed, progress in technology does not mean simply device shortening, which is directly related to gate oxide thinning, doping level change, introduction of highK/metal gate stacks, but in the same time requests an introduction of new solutions for the control of short-channel effects, as e.g. channel engineering (additional HALO or pocket implantation) and various multiple-gates device architectures. This paper summarizes our experimental and simulation results obtained on different advanced technologies [1-7]. We start from fully-depleted (FD) / partially depleted (PD) advanced SOI technologies and finish with multiple-gate MOSFETs (MuGFETs). In this paper the main attention is focused on temperature dependence of two major MOSFET parameters as threshold voltage and subthreshold slope and its evolution with technology advance. We also briefly show some exotic effects in advanced devices and their temperature dependences.  It is demonstrated that advanced devices appear to have a great potential for future high temperature application and are worth of further detailed investigations of their high-temperature stability and reliability.

[1] L. Vancaillie et al. HITEN 2003, pp. 127-132.

[2] L. Vancaillie et al. SOI Conf. 2003, pp. 78-79.

[3] V. Kilchytska et al. ULIS 2004, pp. 163-166.

[4] V. Kilchytska, et al. in NATO ASI Series, Series 2: Mathematics, Physics and Chemistry, Vol. 185, pp.185-190, 2005.

[5] L. Vancaillie et al. HITEN 2005.

[6] V. Kilchytska et al. EuroSOI 2007, pp. 30-31.

[7] V. Kilchytska et al. to be published in SSE, 2007.

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