Quartzdyne Pressure Transducers incorporate circuits that require operation at high temperature, low voltage, and low power.  The next-generation circuit design includes additional features that require more components; to fit in the same space, a higher level of circuit integration was required.  Die component selection is typically limited to a few simple devices; these same parts are becoming unavailable, further limiting the selection.  Experience has shown that reduced component count decreases circuit failures due to high vibrations and mechanical shock while increasing its life.  Using a custom high-temperature ASIC to replace many of the discrete components of these designs would be desirable, if the development costs were reasonable.

High temperature rated SOI and standard bulk CMOS processes were investigated.  The SOI did not meet the design criteria as it would not allow analog circuit design at 2.5V.  Bulk CMOS was shown to enable low voltage analog design for high temperature applications.  The mask costs associated with a 0.8um feature size have become relatively inexpensive; combining this with the availability of small engineering wafer runs provides lower cost small volume ASIC manufacturing.  Using a 0.8um Bulk CMOS process, low-cost CAD tools and well-known high temperature CMOS design techniques, a 225°C rated ASIC was developed, fabricated and tested.

This ASIC (88mil x 92mil) powers the three-crystals of a Quartzdyne Pressure Transducer, providing 3 amplifiers with startup control, 2 mixers with filters, independent bias generators as well as output level translators.  For crystal design flexibility, each oscillator’s gain is adjustable through 2 external tank capacitors and one bias resistor.  The startup control requires one external capacitor for each oscillator. Full circuit functionality was demonstrated -40°C to 245°C.  A new hybrid circuit was developed utilizing this ASIC, it has reduced the overall component counts 40% to 55%.  Because the manufacturing costs have decreased through higher yields and increased throughput, the ASIC development costs have become reasonable.

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