Recently, the metal-nanocrystal embedded in gate dielectric has attracted much attention because of its potential for low power, high speed and high density non-volatile memory application. In order to further improve the program/erase speed and reduce the power consumption, high-dielectric-constant (high-k) materials were adopted to replace SiO2 as the control oxide in nanocrystal floating gate memory. A higher electric field can be induced across the tunnel oxide by using the high-k dielectrics as the control oxide under the same programming voltage. A large hysteresis loop results in the capacitance-voltage (C-V) relation at a low operating voltage. In addition, the gate injection can be avoided due to the lower electric field across the control oxide.

In this work, thermal oxidation and RF magnetron sputtering, sequentially, were used to fabricate MOS capacitors with a layer of Au nanocrystals embedded within a SiO₂/BST (Ba_0.5Sr_0.5TiO₃) stack. A 2.5 or 5-nm-thick dry oxide was grown at 900 °C on p-type, 5-10 Ωcm, (100) silicon substrate. Subsequently, a Au ultrathin film were deposited at room temperature and then BST thin film was deposited at 550°C in situ by RF magnetron sputtering.

The MOS structure was examined by high resolution transmission electron microscopy (HRTEM) to observe the morphology and distribution of nanocrystals. High frequency C-V measurements were used to investigate the charge trapping and detrapping processes in floating gate metal-oxide-semiconductor memory based on Au nanocrystals.

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