Characteristics of the optimized pentacene thin film transistor via OTS treatment of gate insulator and thermal treatment of pentacene layer
|SeongJun Kang , D. S. Park 1, H. J. KIM 1, Kwun-Bum Chung , M. H. Jang 1, M. Noh 1, C. N. Whang 1|
1. Yonsei University (Yonsei UNIV.), Sinchon-dong, Sudaemoon-ku, Seoul 120-749, Korea, South
Pentacene thin film transistor is a promising competitor of amorphous Si-based semiconductor devices though further study is necessary to improve mobility. In our experiment, preferentially oriented high quality pentacene thin film was obtained via thermal evaporation in ultra-high vacuum. To investigate the effect of substrate surface on the pentacene layer formation, pentacene film was prepared on either octadecyltrichlorosilane (OTS) treated SiO2 substrate or untreated SiO2 substrate. The grain size of the pentacene layer and the organic-metal interface roughness were modified through the thermal treatment of the sample evaporated on either substrate surface. Both the OTS treatment and the thermal treatment increase the structural ordering of pentacene molecules in the pentacene layer. The crystallinity of the pentacene film was investigated via the high-resolution synchrotron x-ray diffractometer at the PLS. The roughness of the film was studied by using atomic force microscopy. We obtained the best device performance at the pentacene thin film transistor that was OTS treated as well as annealed. Our investigation results of the electrical properties on the pentacene thin film transistor will be presented.
Presentation: poster at E-MRS Fall Meeting 2003, Symposium B, by SeongJun Kang
See On-line Journal of E-MRS Fall Meeting 2003
Submitted: 2003-05-10 04:46 Revised: 2009-06-08 12:55
|© 1998-2021 pielaszek research, all rights reserved||Powered by the Conference Engine|