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Oxide based TFTs with high-k multicomponent dielectrics

Pedro Barquinha ,  Luis Pereira ,  Gonçalo Gonçalves ,  Rodrigo F. Martins ,  Elvira Fortunato 

Materials Science Department, CENIMAT-IxN and CEMOP-UNINOVA, FCT-UNL, Campus da Caparica, Caparica, Caparica 2829-516, Portugal

Abstract

During the last years, a large number of publications related with oxide based TFTs have appeared. Polycrystalline binary oxides, like ZnO or SnO2, or more recently multicomponent amorphous oxides, like IZO or GIZO, have been the semiconductors responsible for the excellent performance of these TFTs. However, little attention has been given to the dielectric layer development, being most of the TFTs based on “standard” dielectrics, like thermal SiO2 or PECVD SiNx. In this work several high-k gate dielectrics produced without intentional heating by r.f. magnetron sputtering are explored and used to produce TFTs based on GIZO semiconductor. Binary oxides, like Ta2O5 and HfO2, lead to good performing devices: for example, with Ta2O5 high field-effect mobility (µFE) and low threshold voltage (VT) are obtained, ≈40 cm2/Vs and ≈1 V respectively, at the cost of an undesirably high gate leakage current (IG), that can reach 1 µA at VD=VG=15 V, even when 300 nm thick dielectrics are used. The high IG should be related with a non-favorable band offset between GIZO and Ta2O5 (or HfO2) and dielectric crystallization (mainly HfO2). In order to decrease IG, mixtures of the binary oxides referred above with amorphous and high bandgap dielectrics, like SiO2 or Al2O3, are produced by co-sputtering. The TFTs based on these multicomponent dielectrics still present high µFE and low VT: values like 15-30 cm2/Vs and 1.5-3.0 V, respectively, are obtained depending on the composition of the multicomponent dielectric, which is controlled by the r.f. power applied to the SiO2 or Al2O3 target. However, IG decreases considerably, being now possible to obtain values as low as 1 pA at VD=VG=15 V. Top and bottom-gate structures are analyzed, but generally the former leads to worse properties, which is mainly ascribed to the high bombardment at which the GIZO surface (hence, the GIZO/dielectric interface) is exposed during the dielectric deposition in top-gate structures.

 

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Related papers

Presentation: Oral at E-MRS Fall Meeting 2008, Symposium B, by Pedro Barquinha
See On-line Journal of E-MRS Fall Meeting 2008

Submitted: 2008-05-19 20:00
Revised:   2009-06-07 00:48