Low power, high temperature design goals are contrary to commercial CMOS design. Most commercial design effort focuses on reducing die area and increasing speed. Low power, high temperatures, and higher reliability require different design solutions.

Architectures and design techniques to reduce power consumption at high temperature are examined. Fully static CMOS designs are utilized. DC current paths are eliminated by self-timed design. Transition power is reduced by selectively enabling highly capacitive lines.

A case study is a 512x8 embedded RAM. The RAM operates above 300C and consumes less than 3mW.

• Legal notice:
  

  Copyright (c) Pielaszek Research, all rights reserved.
  The above materials, including auxiliary resources, are subject to Publisher's copyright and the Author(s) intellectual rights. Without limiting Author(s) rights under respective Copyright Transfer Agreement, no part of the above documents may be reproduced without the express written permission of Pielaszek Research, the Publisher. Express permission from the Author(s) is required to use the above materials for academic purposes, such as lectures or scientific presentations.
  In every case, proper references including Author(s) name(s) and URL of this webpage: https://science24.com/paper/12261 must be provided.